Asynchronous Router Design for Scalable GALS Networks on Chip

The aggressive scaling of multi-core designs in embedded and desktop domains has lead to the incorporation of scalable networks on chip (NoC) as the physical communication medium. There is a significant demand for low-latency and high-throughput communication via these networks. Heterogeneous designs in embedded applications have additional communication demands including lower power consumed by the network and bridging of different clock domains. Globally asynchronouslocally synchronous (GALS) networks provide an effective solution to these additional demands. This paper describes the design and implementation of an asynchronous on-chip router module; the fundamental building block of true GALS networks.